1. Field of the Invention
Embodiments of the present invention relate generally to the field of semiconductor devices. More particularly, embodiments of the present invention relate to improved semiconductor devices and techniques for fabricating improved semiconductor devices.
2. Description of the Related Art
Currently, the most commonly used transistor for implementing logic devices in integrated circuits is the metal-oxide semiconductor field effect transistor (MOSFET). In particular, the combination of complementary n-type and p-type MOSFETs, a technology known as “CMOS,” allows for the creation of low power logic devices. Because n-MOS and p-MOS devices are connected in series, no drain current flows—except for a small charging current during the switching process between two different states. Furthermore, improved fabrication techniques have, over the years, led to the reduction of MOSFET sizes through a technique known as “scaling,” which has led to smaller, more densely packed, and faster chips.
More recently, however, the speed benefits typically associated with scaling have diminished due to fundamental physical constraints inherent in MOSFETs. For example, in order to switch the voltage state of a MOSFET, the MOSFETs gate terminal must be sufficiently charged. The amount of charge that will switch the MOSFET on is proportional to the capacitance of the MOSFET's gate terminal. One consequence of scaling is that the thickness of the gate insulator must be reduced to maintain acceptably small short-channel effects. Furthermore, to counteract the increased leakage current that may result from the reduced dielectric thickness and thereby keep the gate leakage current below acceptable levels, the gate insulator may be made of a dielectric with a dielectric constant, “k,” higher than that of silicon dioxide, whose k equals 3.9. Both the reduced thickness and the higher dielectric constant result in higher capacitance. Therefore, although the maximum drain current may increase for the scaled CMOS device, this benefit is largely limited by the increased capacitance. The result is that although the density of CMOS devices continues to increase, the speed performance of such devices has not increased substantially over the generations.
Junction field effect transistors (JFETs), on the other hand, do not utilize an insulated gate. Rather, in a typical JFET, the gate is a p-doped or n-doped semiconductor material and the gate directly contacts the semiconductor body, forming a p-n junction between the gate and the transistor's conductive channel. Because JFETs do not utilize an insulated gate, the total gate capacitance in a JFET may be greatly reduced, which may result in a higher transistor switching speed compared to existing CMOS technology.
However, typical JFETs have limited applicability due to the low forward-bias turn-on voltage, i.e. the diode turn-on voltage, of the p-n junction between the gate and the channel of the JFET. In a typical JFET, the depletion region at the gate-channel interface prevents conduction when the gate potential is sufficiently low. To turn on the JFET, the gate potential is raised, which narrows the depletion region, allowing current to flow between the source and the drain. When the gate potential is raised above the forward bias potential of the p-n junction between the gate and the channel (typically 0.6 to 0.7 volts), current then starts to flow from the gate to the drain. This greatly increases the power consumption of the device. There is a limit, therefore, to the voltage that may be applied to a JFET. As a result, typical prior art JFETs may not be suitable in systems or devices which utilize a high voltage relative to the diode turn-on voltage of the JFET.
Therefore, it may be advantageous to provide an improved low-power semiconductor device with reduced gate capacitance and faster switching speed compared to existing CMOS technology. Specifically, it may be advantageous to provide a JFET with improved electrical characteristics that address the limitations discussed above.